verify instruction

`verify` instruction
	Testing

Description

The verify instruction is used to verify (or to approve) a software component test case. This is typically done by comparing the real result of the test case with an expected result.

The verify instruction can only be used in test scripts (see the section called “test script”) and it is typically executed after a test instruction.

The verification consists of an expression of type yes_no that evaluates to yes if the test passes, or to no if the test fails.

Syntax

Table 20.29. verify syntax

Production	Syntax	Links
`verify_instruction`	`"verify" condition error_info ?`	the section called “`verify` instruction”
`condition`	`-> expression -> expression "compare" comparison_operator expression`	the section called “`condition`”
`error_info`	`( "error_message" ":" expression ) ? ( "error_id" ":" identifier ) ? ( "error_data" ":" expression ) ?`	the section called “`error info`”

condition is an expression of type yes_no that evaluates to yes if the test passes, or to no if the test fails. For more information, see the section called “condition”
error_info is an optional clause used to create more specific error data if the verification failed. For more information, see the section called “error info”

Examples

see: